
Preliminary Information
MT9071
19
1.0
Device Overview............................................................................................................25
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10 Common Channel Signaling...................................................................................................................26
1.11 HDLC......................................................................................................................................................27
1.12 Performance Monitoring and Debugging................................................................................................27
1.13 Interrupts................................................................................................................................................27
Standards Compliance...........................................................................................................................25
Microprocessor Port...............................................................................................................................25
LIU..........................................................................................................................................................25
Reference Switching PLL.......................................................................................................................25
Slip Buffers.............................................................................................................................................25
Interface to the System Backplane.........................................................................................................26
Framing Modes ......................................................................................................................................26
Access to the Maintenance Channel......................................................................................................26
Robbed Bit Signaling / Channel Associated Signaling...........................................................................26
2.0
Line Interface Unit (LIU)................................................................................................27
2.1
2.2
LIU Receiver...........................................................................................................................................27
LIU Transmitter.......................................................................................................................................28
3.0
Timing.............................................................................................................................28
3.1
Timing Modes of Operation....................................................................................................................28
3.1.1
Bus Synchronization Mode............................................................................................................. 29
3.1.2
Free-Run Mode .............................................................................................................................. 30
3.1.3
Line Synchronization Mode............................................................................................................ 31
3.1.4
External Synchronization Mode...................................................................................................... 31
3.1.5
Auto-Holdover Mode....................................................................................................................... 32
3.1.6
Holdover Mode............................................................................................................................... 32
3.2
Remote Loopback..................................................................................................................................33
3.3
Reference Switching ..............................................................................................................................35
3.4
PLL State Changes................................................................................................................................35
3.5
Master Clock ..........................................................................................................................................36
3.6
Auxiliary Output SIgnals.........................................................................................................................36
4.0
Interface and Framing...................................................................................................37
4.1
T1 Interface Overview............................................................................................................................37
4.1.1
T1 Encoding and Decoding Options............................................................................................... 38
4.1.2
T1 Pulse Density ............................................................................................................................ 39
4.2
T1 Frame Alignment...............................................................................................................................39
4.3
T1 Reframe ............................................................................................................................................39
4.4
T1 Multiframing.......................................................................................................................................40
4.4.1
T1 D4 Multiframing......................................................................................................................... 40
4.4.2
T1 T1DM Mode............................................................................................................................... 41
4.4.3
T1 ESF Multiframing....................................................................................................................... 42