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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 49/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
49
6.0
Slip Buffers and Jitter Attenuators
6.1
T1 Slip Buffer
In T1 mode MT9071 contains two sets of slip buffers, one on the transmit side, and one on the receive side.
Both sides may perform a controlled slip. The mechanisms that govern the slip function are a function of
backplane timing and the mapping between the ST-BUS channels and the DS1 channels. The slip mechanisms
are different for the transmit and receive slip buffers. The extracted 1.544 MHz clock (RxCK) and the internally
generated transmit 1.544 MHz clock are distinct. Slips on the transmit side are independent from slips on the
receive side.
6.1.1
The transmit slip buffer has data written to it from the near end 2.048 Mb/s stream. The data is clocked out of
the buffer using signals derived from the internal transmit 1.544 MHz clock. The transmit 1.544 MHz clock is
always phase locked to the DSTi 2.048 Mb/s stream. If the system backplane clock (CKb is an output) is
internally generated, then it is hard locked to the 1.544 MHz clock. No phase drift or wander can exist between
the two signals - therefore no slips will occur. The delay through the transmit elastic buffer is then fixed, and is
a function of the relative mapping between the DSTi channels and the DS1 timeslots. These delays vary with
the position of the channel in the frame. For example, DS1 timeslot 1 sits in the elastic buffer for approximately
1us and DS1 timeslot 24 sits in the elastic buffer for approximately 32us. Note that the system backplane clock
(CKb) is internally generated for all timing modes except Bus Sync mode, see Table 1 - E1 and T1 Timing
Modes Summary.
T1 Transmit Slip Buffer
Figure 11 - Read and Write Pointers in the T1 Transmit Slip Buffers
If the system backplane clock (CKb) is externally generated, the transmit 1.544 MHz clock is phase locked to it,
but the PLL is designed to filter jitter present in the CKb clock. As a result phase drift will result between the two
signals. The delay through the transmit elastic buffer will vary in accordance with the input clock drift, as well as
being a function of the relative mapping between the DSTi channels and the DS1 timeslots. If the read pointers
approach the write pointers (to within approximately 1us) or the delay through the transmit buffer exceeds
Write
Pointer
221us
4us
188us
62us
129us
512 Bit
Elastic
Store
92us
92us
Wander Tolerance
Read Pointer
Read Pointer
Read Pointer
Read Pointer
0us
Frame 0
Frame 1
Frame 0
Frame 1
Frame 0
Frame 1
Write Vectors
Read Vectors
Minimum Delay
Read Vectors - Maximum Delay
96us
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch(大數(shù)字開(kāi)關(guān)) |
| MT90823 | 3V Large Digital Switch(3V 大數(shù)字開(kāi)關(guān)) |
| MT90826 | Quad Digital Switch(四數(shù)字開(kāi)關(guān)) |
| MT90840 | Distributed Hyperchannel Switch(分布式超級(jí)通道開(kāi)關(guān)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT90710AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
| MT9072 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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