
MT9071
Preliminary Information
154
4
CASRL
Receive Channel Associated Signaling (CAS) Change Latch.
When any of the receive
CAS (i.e. ABCD) bits in the E1 Receive CAS Data Registers - R Address Y71-Y7F, Y81-Y8F
change state, this status bit is latched to one. This bit is set on a basic frame (FPb) basis. It is
cleared when either this register, or the E1 National Interrupt Status - R Address Y36 is read.
CRC-4 Alignment 2ms Timer Latch.
When the CALN status bit (E1 Synchronization & CRC-
4 Remote Status - R Address Y10) toggles from zero to one, this status bit is latched to one.
This bit is set on a 2ms or CRC-4 multiframe frame basis. It is cleared when either this
register, or the E1 National Interrupt Status - R Address Y36 is read.
Timer 2 Latch.
When the CRC-4 T2 (10ms) status bit (E1 CRC-4 Timers & CRC-4 Local
Status - R Address Y11) toggles from zero to one, this status bit is latched to one. This bit is
set on a basic frame (FPb) basis. It is cleared when either this register, or the E1 National
Interrupt Status - R Address Y36 is read.
Timer 1 Latch.
When the CRC-4 T1 (100ms) status bit (E1 CRC-4 Timers & CRC-4 Local
Status - R Address Y11) toggles from zero to one, this status bit is latched to one. This bit is
set on a basic frame (FPb) basis. It is cleared when either this register, or the E1 National
Interrupt Status - R Address Y36 is read.
ONESECL
One Second Timer Status Latch.
When the ONESEC status bit (E1 CRC-4 Timers & CRC-4
Local Status - R Address Y11) toggles from zero to one, this status bit is latched to one. This
bit is set on a basic frame (FPb) basis. It is cleared when either this register, or the E1 National
Interrupt Status - R Address Y36 is read.
Table 137 - E1 National Latched Status - R Address Y26
3
CALNL
2
T2L
1
T1L
0
Bit
Name
Functional Description
15-4 (#### #### ###) Not Used
3
RAIP
Remote Alarm Indication Status Persistent Latch.
When the RAI (A) status bit (E1
Alarms & MAS Status - R Address Y12) toggles from zero to one, this status bit is latched
to one. This bit is cleared when this register is read while the RAI status bit is zero.
Alarm Indication Status Signal Persistent.
When the AIS status bit (E1 Alarms & MAS
Status - R Address Y12) toggles from zero to one, this status bit is latched to one. This bit
is cleared when this register is read while the AIS status bit is zero.
Loss of Signal Status Indication Persistent Latch.
When the LOSS status bit (E1
Alarms & MAS Status - R Address Y12) toggles from zero to one, this status bit is latched
to one. This bit is cleared when this register is read while the LOSS status bit is zero.
Receive Basic Frame Alignment Persistent Latch.
When the BSYNC status bit (E1
Synchronization & CRC-4 Remote Status - R Address Y10) toggles from zero to one, this
status bit is latched to one. This bit is cleared when this register is read while the BSYNC
status bit is zero.
Table 138 - E1 Persistent Latched Status - R Address Y27
2
AISP
1
LOSSP
0
BSYNCP
Bit
Name
Functional Description