
MOTOROLA
Chapter 8. Internal Control
8-7
8.1.3.1 PCI-Read-from-System-Memory Buffer (PCMRB)
When a PCI device initiates a read from system memory, the address is snooped on the 60x
processor bus. The memory access is started simultaneous with the snoop. If the snoop
results in a hit in either the L1 or L2 cache, the MPC105 cancels the system memory access.
Depending on the outcome of the snoop, the requested data is latched into either the 32-
byte PCI-read-from-system-memory buffer (PCMRB), or into the copy-back buffer (as
described in Section 8.1.1, “60x Processor/System Memory Buffers”).
If the snoop hits in the L1, the copy-back data is written to the copy-back buffer,
forwarded to PCI, and then written to memory when the PCI transfer is complete.
If the snoop hits in the L2, the data is written to the PCMRB and sent to PCI without
changing the internal state of the data in the L2. Note that a copy-back to system
memory is unnecessary because the state of the data in the L2 remains unchanged.
If the snoop does not hit in either the L1 or L2, the PCMRB is filled from system
memory starting at the requested address to the end of the cache line.
The data is forwarded to PCI as soon as it is received, not when the complete cache line has
been written into the PCMRB. The addresses for subsequent PCI reads are compared to the
existing address, so if the new access falls within the same cache line and the requested data
is already latched in the buffer, the data can be forwarded to PCI without requiring a snoop
or another memory transaction.
If a PCI write address hits in the PCMRB, the buffer is invalidated and the address is
snooped on the processor bus. If the 60x processor accesses the address in the PCMRB, the
PCMRB is invalidated.
8.1.3.2 PCI-to-System-Memory-Write Buffers (PCMWBs)
For PCI write transactions to system memory, the MPC105 employs two PCMWBs. The
PCMWBs hold up to one cache line (32-bytes) each. Before PCI data is transferred to
system memory, the address must be snooped on the 60x processor bus. The buffers allow
for the data to be latched while waiting for a snoop response. The write data can be accepted
without inserting wait states on the PCI bus. Also, two buffers allow a PCI master to write
to one buffer, while the other buffer is flushing its contents to system memory. Both
PCMWBs are capable of gathering for writes to the same cache line.
If the snoop on the 60x processor bus hits modified data in either the L1 or L2 cache, the
snoop copy-back data is merged with the data in the PCMWB, and the full cache line is sent
to memory. For the PCI memory-write-and-invalidate command, a snoop hit in either the
L1 or L2 cache invalidates any modified cache line without requiring a copy-back.
Note that a PCI transaction that hits in either of the PCMWBs does not require a snoop on
the 60x processor bus. However, if a PCI write address hits in the PCI-read-from-system-
memory buffer (PCMRB), the MPC105 invalidates the PCMRB and snoops the address on
the 60x processor bus.