
MOTOROLA
Chapter 7. PCI Bus Interface
7-3
The target interface uses the fastest device selection timing and can accept burst writes to
system memory of up to 32 bytes with no wait states. Burst reads from system memory are
also accepted with wait states inserted depending upon the device timing of system
memory. The target interface disconnects when a transaction reaches the end of a cache line
(32-bytes) so a new address can be provided to snoop the 60x bus.
7.2 PCI Bus Arbitration
The PCI arbitration approach is access-based. Bus masters must arbitrate for each access
performed on the bus. PCI uses a central arbitration scheme where each master has its own
unique request (REQ) and grant (GNT) signal. A simple request-grant handshake is used to
gain access to the bus. Arbitration for the bus occurs during the previous access so that no
PCI bus cycles are consumed due to arbitration (except when the bus is idle).
The MPC105 does not function as the central PCI bus arbiter. It is the responsibility of the
system designer to provide for PCI bus arbitration. Regardless of the implementation, the
arbitration algorithm must be defined to establish a basis for a worst-case latency guarantee.
Latency guidelines are provided in the
PCI Local Bus Specification
. There are devices
available that integrate the central arbiter, DMA controller, interrupt controller, and PCI-to-
ISA bridge functions into a single device.
7.2.1 Exclusive Access
PCI provides an exclusive access mechanism referred to as a resource lock. The mechanism
locks only the selected PCI resource but allows other nonexclusive accesses to proceed. A
full description of exclusive access is contained in the
PCI Local Bus Specification
.
The LOCK signal indicates an exclusive access is underway. The assertion of GNT does
not guarantee control of the LOCK signal. Control of LOCK is obtained in conjunction
with GNT. When using resource lock, agents performing nonexclusive accesses are free to
proceed even while another master retains ownership of LOCK.
The MPC105 implements the LOCK signal to guarantee complete access exclusion in
system memory. The 60x processor must honor the resource lock. If a master on the PCI
bus asserts LOCK for a transaction to system memory, the MPC105 flushes all internal
PCI-to-memory write buffers, performs a snoop transaction on the 60x bus, prevents
masters on the 60x bus from starting any new transactions (except for a snoop copy-back),
and then completes the locked transaction. The 60x bus remains locked as long as the
MPC105 is locked and the LOCK signal is asserted.
7.3 PCI Bus Protocol
This section provides a general description of the PCI bus protocol by presenting the basic
transfer control mechanisms. Specific PCI bus transactions are described in Section 7.4,
“PCI Bus Transactions.” Refer to Figure 7-1 and Figure 7-2 for examples of the transfer
control mechanisms described in this section.