
MOTOROLA
Chapter 7. PCI Bus Interface
7-15
7.4.5.2 Accessing the PCI Configuration Space
To support hierarchical bridges, two types of configuration accesses are supported. The first
type of configuration access, type 0, is used to select a device on the local PCI bus (the PCI
bus connected to the MPC105). Type 0 configuration accesses are not propagated beyond
the local PCI bus and must be claimed by a local device or terminated with a master-abort.
The second type of configuration access, type 1, is used to pass a configuration request on
to another PCI bus (through a PCI-to-PCI bridge). Type 1 accesses are ignored by all targets
except PCI-to-PCI bridges.
To access the configuration space, a 32-bit value must be written to the CONFIG_ADDR
register that specifies the target PCI bus, the target device on that bus, and the configuration
register to be accessed within that device. A read or write to the CONFIG_DATA register
causes the MPC105 to translate the access into a PCI configuration cycle (provided the
enable bit in CONFIG_ADDR is set and the device number is not 0b1_1111).
The CONFIG_ADDR register is located at different addresses depending on the memory
address map in use. The address maps are described in Section 3.1, “Address Maps.” For
address map A in the contiguous mode, the 60x can access the CONFIG_ADDR register
through the MPC105 at 0x8000_0CF8. For address map A in the discontiguous mode, the
60x can access the CONFIG_ADDR register through the MPC105 at 0x8006_7018. For
address map B, the 60x can access the CONFIG_ADDR register at any location in the
address range from 0xF080_0000 to 0xF0BF_FFFF. For simplicity, the address for
0E
Header type
Bits 0–6 identify the layout of bytes 10-3F; bit 7 indicates a multifunction
device. The most common header type (0x00) is shown in Figure 7-3
and in this table.
0F
BIST
Optional register for control and status of built-in self test (BIST)
10–27
Base address registers
Address mapping information for memory and I/O space
28
—
Reserved for future use
2C
—
Reserved for future use
30
Expansion ROM base
address
Base address and size information for expansion ROM contained in an
add-on board
34
—
Reserved for future use
38
—
Reserved for future use
3C
Interrupt line
Contains interrupt line routing information
3D
Interrupt pin
Indicates which interrupt pin the device (or function) uses
3E
Min_Gnt
Specifies the length of the device’s burst period in 0.25
μ
s units
3F
Max_Lat
Specifies how often the device needs to gain access to the bus in 0.25
μ
s units
Table 7-2. PCI Configuration Space Header Summary (Continued)
Address
Offset
Register Name
Description