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MPC105 PCIB/MC User’s Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
Appendix A
Power Management
A.1
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.2
A.2.1
A.2.2
A.2.3
A.2.4
A.2.5
A.2.6
A.2.7
MPC105 Power Modes.......................................................................................A-1
MPC105 Power Mode Transition...................................................................A-1
Full-On Mode .................................................................................................A-3
Doze Mode......................................................................................................A-3
Nap Mode .......................................................................................................A-3
Sleep Mode.....................................................................................................A-4
Suspend Mode.................................................................................................A-5
MPC105 Power Management Support...............................................................A-6
Power Management Configuration Register...................................................A-6
Clock Configuration .......................................................................................A-6
PCI Address Bus Decoding ............................................................................A-7
PCI Bus Special-Cycle Operations.................................................................A-7
Processor Bus Request Monitoring.................................................................A-7
Memory Refresh Operations in Sleep/Suspend Mode....................................A-7
Device Drivers................................................................................................A-8
Appendix B
Bit and Byte Ordering
B.1
B.2
Big-Endian Mode.................................................................................................B-1
Little-Endian Mode..............................................................................................B-4
Appendix C
JTAG/Testing Support
C.1
C.1.1
C.1.2
C.1.2.1
C.1.2.2
C.1.2.3
C.1.3
JTAG Interface Description.................................................................................C-1
JTAG Signals...................................................................................................C-2
JTAG Registers and Scan Chains....................................................................C-2
Bypass Register......................................................................................C-2
Boundary-Scan Registers.......................................................................C-2
Instruction Register................................................................................C-3
TAP Controller ................................................................................................C-3
Appendix D
Initialization Example
Glossary of Terms and Abbreviations
INDEX