
766
TCSR0—Timer Control/Status Register
H'FF74(W)
H'FF74(R)
WDT0
7
OVF
0
R/(W)*
6
WT/
IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
TCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
Note: * For details of the case where TCNT overflows in watchdog timer mode,
see section 11.2.3, Reset Control/Status Register (RSTCSR).
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
Timer Enable
0
1
TCNT is initialized to H'00 and
count operation is halted
TCNT counts
Timer Mode Select
0
1
Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when
TCNT overflows
Watchdog timer mode: Internal reset can be selected when TCNT overflows*
Overflow Flag
0
1
[Clearing conditions]
Overflow Flag
Read TCSR when OVF = 1, then write 0 in OVF
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.
Clock Select 2 to 0
Clock
Overflow Period*
(when = 10 MHz)
/2 (Initial value)
51.2
s
/64
1.6 ms
/128
3.2 ms
/512
13.2 ms
/2048
52.4 ms
/8192
209.8 ms
/32768
838.8 ms
/131072
3.36 s
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CKS2 CKS1 CKS0