
746
TIOR0L—Timer I/O Control Register 0L
H'FF13
TPU0
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
0
IOC0
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
Note: *1 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a
buffer register, this setting is invalid and input capture/output compare
is not generated.
Bit
Initial value
R/W
:
Note: *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer
register, this setting is invalid and input capture/output compare is not
generated.
I/O Control C3 to C0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0
1
*: Don’t care
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source
isTIOCC0 pin
Setting prohibited
TGR0C is
output
compare
register*1
TGR0C is
input capture
register*1
I/O Control D3 to D0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0
1
*: Don’t care
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source is
TIOCD0 pin
Setting prohibited
TGR0D is
output
compare
register*1
TGR0D is
input capture
register*1
Note:
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.