
782
SCR2—Serial Control Register 2
H'FF8A
SCI2
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
R/W
:
Transmit End Interrupt Enable
0
1
Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit Enable
0
1
Transmission disabled
Transmission enabled
Receive Enable
0
1
Reception disabled
Reception enabled
Transmit Interrupt Enable
0
1
Transmit data empty interrupt (TXI) requests disabled
Transmit data empty interrupt (TXI) requests enabled
Receive Interrupt Enable
0
1
Receive data full interrupt (RXI) request and receive error
interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error
interrupt (ERI) request enabled
Multiprocessor Interrupt Enable
0
1
Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
When the MPIE bit is cleared to 0
When MPB= 1 data is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and settingof the RDRF, FER, and ORER flags in SSR
are disabled until data with the multiprocessor bit set to 1 is received.
Clock Enable 1 and 0
0
1
0
1
0
1
Asynchronous mode
Internal clock/SCK pin
functions as I/O port
Clocked synchronous mode
Internal clock/SCK pin
functions as serial clock output
Asynchronous mode
Internal clock/SCK pin
functions as clock output*
1
Clocked synchronous mode
Internal clock/SCK pin
functions as serial clock output
Asynchronous mode
External clock/SCK pin
functions as clock input*
2
Clocked synchronous mode
External clock/SCK pin
functions as serial clock input
Asynchronous mode
External clock/SCK pin
functions as clock input*
2
Clocked synchronous mode
External clock/SCK pin
functions as serial clock input
Notes: *1
*2
Outputs a clock of the same frequency as the bit rate.
Inputs a clock with a frequency 16 times the bit rate.