
xvi
Figure 7-19
Example of Full Address Mode (Block Transfer Mode) Transfer ...................... 223
Figure 7-20
Example of
DREQ Pin Falling Edge Activated Normal Mode Transfer............. 224
Figure 7-21
Example of
DREQ Pin Falling Edge Activated Block Transfer Mode Transfer. 225
Figure 7-22
Example of
DREQ Level Activated Normal Mode Transfer .............................. 226
Figure 7-23
Example of
DREQ Level Activated Block Transfer Mode Transfer .................. 227
Figure 7-24
Example of Multi-Channel Transfer.................................................................... 228
Figure 7-25
Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt.................................................................................................. 230
Figure 7-26
Example of Procedure for Forcibly Terminating DMAC Operation ................... 231
Figure 7-27
Example of Procedure for Clearing Full Address Mode...................................... 232
Figure 7-28
Block Diagram of Transfer End/Transfer Break Interrupt .................................. 233
Figure 7-29
DMAC Register Update Timing.......................................................................... 234
Figure 7-30
Contention between DMAC Register Update and CPU Read ............................. 235
Figure 8-1
Block Diagram of DTC........................................................................................ 238
Figure 8-2
Flowchart of DTC Operation ............................................................................... 247
Figure 8-3
Block Diagram of DTC Activation Source Control ............................................ 249
Figure 8-4
Correspondence between DTC Vector Address and Register Information ......... 252
Figure 8-5
Location of Register Information in Address Space............................................ 253
Figure 8-6
Memory Mapping in Normal Mode..................................................................... 254
Figure 8-7
Memory Mapping in Repeat Mode...................................................................... 255
Figure 8-8
Memory Mapping in Block Transfer Mode ......................................................... 256
Figure 8-9
Chain Transfer Memory Map .............................................................................. 257
Figure 8-10
DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 258
Figure 8-11
DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) .................................. 258
Figure 8-12
DTC Operation Timing (Example of Chain Transfer) ........................................ 259
Figure 9-1
Port 1 Pin Functions ............................................................................................. 269
Figure 9-2
Port 3 Pin Functions ............................................................................................. 280
Figure 9-3
Port 4 Pin Functions ............................................................................................. 287
Figure 9-4
Port 7 Pin Functions ............................................................................................. 291
Figure 9-5
Port 9 Pin Functions ............................................................................................. 297
Figure 9-6
Port A Pin Functions............................................................................................ 298
Figure 9-7
Port B Pin Functions ............................................................................................ 305
Figure 9-8
Port C Pin Functions ............................................................................................ 313
Figure 9-9
Port C Pin Functions (Modes 4 and 5) ................................................................. 316
Figure 9-10
Port C Pin Functions (Mode 6) ............................................................................ 317
Figure 9-11
Port C Pin Functions (Mode 7) ............................................................................ 317
Figure 9-12
Port D Pin Functions............................................................................................ 319
Figure 9-13
Port D Pin Functions (Modes 4 to 6) ................................................................... 322
Figure 9-14
Port D Pin Functions (Mode 7)............................................................................ 323
Figure 9-15
Port E Pin Functions ............................................................................................ 324
Figure 9-16
Port E Pin Functions (Modes 4 to 6).................................................................... 327
Figure 9-17
Port E Pin Functions (Mode 7) ............................................................................ 328