
756
TCR2—Timer Control Register 2
H'FF30
TPU2
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Bit
Initial value
R/W
:
Time Prescaler 2 to 0
Internal clock: counts on /1
Internal clock: counts on /4
Internal clock: counts on /16
Internal clock: counts on /64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on /1024
0
1
Note: This setting is ignored when channel 2 is in phase
counting mode.
0
1
0
1
0
1
0
1
0
1
0
1
Clock Edge 1 and 0
Count at rising edge
Count at falling edge
Count at both edges
0
1
Note: The internal clock edge selection is valid when the input clock is
/4 or slower. This setting is ignored if the input clock is /1, or
when overflow/underflow of another channel is selected.
0
1
—
Counter Clear 2 to 0
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*2
0
1
0*1
Notes: *1
*2
Bit 7 is reserved.
It cannot be modified and is alway read as 0.
Synchronous operation setting is performed by setting
the SYNC bit in TSYR to 1.
0
1
0
1