
460
Bits 2 to 0—Asynchronous Clock Source Select 2 to 0 (ACS2 to ACS0): These bits select the
clock source in asynchronous mode.
When an average transfer rate is selected, the base clock is set automatically regardless of the
ABCS value. Note that average transfer rates are not supported for operating frequencies other
than 10.667 MHz and 16 MHz.
The setting in bits ACS2 to ACS0 is valid when external clock input is used (CKE1 = 1 in SCR) in
asynchronous mode (C/
A = 0 in SMR). The setting in ACS2 to ACS0 is invalid when an internal
clock is selected (CKE1 = 0 in SCR) in asynchronous mode, or when the chip is in synchronous
mode (C/
A = 1 in SMR).
Bit 2
Bit 1
Bit 0
ACS2
ACS1
ACS0
Description
0
External clock input
(Initial value)
1
115.152 kbps average transfer rate (for = 10.667 MHz only)
is selected (SCI0 operates on base clock with frequency of
16 times transfer rate)
1
0
460.606 kbps average transfer rate (for = 10.667 MHz only)
is selected (SCI0 operates on base clock with frequency of 8
times transfer rate)
1
Reserved
1
0
TPU clock input (AND of TIOCA1 and TIOCA2)
1
115.196 kbps average transfer rate (for = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 16
times transfer rate)
1
0
460.784 kbps average transfer rate (for = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 16
times transfer rate)
1
720 kbps average transfer rate (for = 16 MHz only) is
selected (SCI0 operates on base clock with frequency of 8
times transfer rate)