
xxvi
Table 18-9
Timing of On-Chip Supporting Modules............................................................. 620
Table 18-10
DMAC Timing ..................................................................................................... 623
Table 18-11
D/A Conversion Characteristics .......................................................................... 624
Table 18-12
Flash Memory Characteristics ............................................................................. 625
Table A-1
Data Transfer Instructions.................................................................................... 629
Table A-2
Arithmetic Instructions ........................................................................................ 632
Table A-3
Logical Instructions.............................................................................................. 636
Table A-4
Shift Instructions.................................................................................................. 637
Table A-5
Bit-Manipulation Instructions.............................................................................. 640
Table A-6
Branch Instructions .............................................................................................. 645
Table A-7
System Control Instructions................................................................................. 648
Table A-8
Block Transfer Instructions.................................................................................. 650
Table A-9
Instruction Codes ................................................................................................. 651
Table A-10
Operation Code Map (1) ...................................................................................... 665
Table A-11
Operation Code Map (2) ...................................................................................... 666
Table A-12
Operation Code Map (3) ...................................................................................... 667
Table A-13
Operation Code Map (4) ...................................................................................... 668
Table A-14
Number of States per Cycle ................................................................................. 670
Table A-15
Number of Cycles in Instruction Execution......................................................... 671
Table A-16
Instruction Execution Cycles ............................................................................... 685
Table A-17
Condition Code Modification .............................................................................. 698
Table D-1
I/O Port States in Each Processing State.............................................................. 822
Table F-1
H8S/2214 Product Code Lineup .......................................................................... 826