
745
TIOR0H—Timer I/O Control Register 0H
H'FF12
TPU0
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Bit
Initial value
R/W
:
Note:
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
I/O Control A3 to A0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0
1
*: Don’t care
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source
isTIOCA0 pin
Setting prohibited
TGR0A is
output
compare
register
TGR0A is
input capture
register
I/O Control B3 to B0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0
1
*: Don’t care
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source
isTIOCB0 pin
Setting prohibited
TGR0B is
output
compare
register
TGR0B is
input capture
register