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6.3.4
Interface Specifications for Each Area
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (6.4 and 6.5) should be referred to for further
details.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the
CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space.
When area 1 to 6 external space is accessed, the
CS1 to CS6 pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 to 6.
Area 7: Area 7 includes the on-chip RAM, external module expansion function space, and internal
l/O registers. In external expansion mode, the space excluding the on-chip RAM, external module
expansion function space, and internal l/O registers, is external space. The on-chip RAM is
enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME
bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external
space.
When the P75MSOE bit in the external module connection output pin select register (OPINSEL)
is set to 1, the external module expansion function is enabled and the signal is output for addresses
H'FFFF40 to H'FFFF5F. When the P75MSOE bit is cleared to 0, the external module expansion
function is disabled and the corresponding addresses are external space.
When area 7 external space is accessed, the
CS7 signal can be output.
Only the basic bus interface can be used for the area 7.