
v
7.1.1
Features ................................................................................................................. 163
7.1.2
Block Diagram ...................................................................................................... 164
7.1.3
Overview of Functions.......................................................................................... 165
7.1.4
Pin Configuration .................................................................................................. 167
7.1.5
Register Configuration .......................................................................................... 168
7.2
Register Descriptions (1) (Short Address Mode) ............................................................... 169
7.2.1
Memory Address Registers (MAR) ...................................................................... 170
7.2.2
I/O Address Register (IOAR)................................................................................ 171
7.2.3
Execute Transfer Count Register (ETCR) ............................................................ 171
7.2.4
DMA Control Register (DMACR)........................................................................ 172
7.2.5
DMA Band Control Register (DMABCR)............................................................ 176
7.3
Register Descriptions (2) (Full Address Mode) ................................................................. 181
7.3.1
Memory Address Register (MAR)........................................................................ 181
7.3.2
I/O Address Register (IOAR)................................................................................ 181
7.3.3
Execute Transfer Count Register (ETCR) ............................................................ 182
7.3.4
DMA Control Register (DMACR)........................................................................ 183
7.3.5
DMA Band Control Register (DMABCR)............................................................ 187
7.4
Register Descriptions (3).................................................................................................... 192
7.4.1
DMA Write Enable Register (DMAWER) ........................................................... 192
7.4.2
DMA Terminal Control Register (DMATCR)...................................................... 194
7.4.3
Module Stop Control Register A (MSTPCRA) .................................................... 195
7.5
Operation ............................................................................................................................ 196
7.5.1
Transfer Modes ..................................................................................................... 196
7.5.2
Sequential Mode.................................................................................................... 198
7.5.3
Idle Mode .............................................................................................................. 201
7.5.4
Repeat Mode ......................................................................................................... 204
7.5.5
Normal Mode ........................................................................................................ 208
7.5.6
Block Transfer Mode ............................................................................................ 211
7.5.7
DMAC Activation Sources ................................................................................... 217
7.5.8
Basic DMAC Bus Cycles...................................................................................... 219
7.5.9
DMAC Bus Cycles (Dual Address Mode)............................................................ 220
7.5.10 DMAC Multi-Channel Operation ......................................................................... 227
7.5.11 Relation between the DMAC, External Bus Requests, and the DTC ................... 229
7.5.12 NMI Interrupts and DMAC................................................................................... 230
7.5.13 Forced Termination of DMAC Operation............................................................. 231
7.5.14 Clearing Full Address Mode ................................................................................. 232
7.6
Interrupts ............................................................................................................................ 233
7.7
Usage Notes........................................................................................................................ 234
Section 8
Data Transfer Controller (DTC) ................................................................. 237
8.1
Overview ............................................................................................................................ 237
8.1.1
Features ................................................................................................................. 237
8.1.2
Block Diagram ...................................................................................................... 238