
Section
Title
Page
Revisions
(See Manual for Details)
Section 7
7.5
Operation
—
7.5.5 Single Address Mode deleted.
DMA
Controller
—
7.5.11 DMAC Bus Cycles (Single
Address Mode) deleted.
—
7.5.12 Write Data Buffer Function
deleted.
7.5.1
Transfer Modes
196
Table 7-6 DMAC Transfer Modes
Single Address Mode deleted. Note
revise.
—
Description of Single Address Mode
deleted.
7.5.7
DMAC Activation
Sources
—
Description of Single Address Mode
deleted.
7.5.11
Relation between the
DMAC, External Bus
Requests, and the DTC
229
Description of Refresh Cycle
deleted.
7.7
Usage Notes
235
Module Stop
Description of DACK pin enable
(FAE=0 and SAE=1) deleted.
—
Write data buffer function deleted.
Section 9 I/O
Ports
9.1
Overview
266
Table 9-1 H8S/2214 Port Functions
Description of port 1 DMAC output
pins (DACK0 and DACK1) deleted.
269
Description of DMAC output pins
(DACK0 and DACK1) related to port
1 deleted.
Section 10
16-Bit Timer
Pulse Unit
(TPU)
10.1.2
Block Diagram
345
Figure 10-1 Block Diagram of
H8S/2214 TPU
A/D conversion start request signal
deleted.
Section 11
Watchdog
Timer (WDT)
11.2.2
Timer Control/Status
Register (TCSR)
419
Table Bit 7: Overflow Flag (OVH)
amended and Note added.
11.2.4
Notes on Register
Access
422
Writing to RSTCSR
H'FFBB in description changed to
H'FF76.