
1
Section 1 Overview
1.1
Overview
The H8S/2214 is a microcomputer (MCU: microcomputer unit), built around the H8S/2000 CPU,
employing Hitachi's proprietary architecture, and equipped with the on-chip peripheral functions
necessary for system configuration.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller (DMAC)
data transfer controller (DTC) bus masters, ROM and RAM memory, a16-bit timer-pulse unit
(TPU), watchdog timer (WDT), serial communication interface (SCI), D/A converter, and I/O
ports.
The on-chip ROM is either flash memory (F-ZTAT*) or mask ROM, with a capacity of 128
kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to
be accessed in one state. Instruction fetching has been speeded up, and processing speed increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2214 are shown in Table 1-1.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.