
331
9.12.2
Register Configuration
Table 9-22 shows the port F register configuration.
Table 9-22 Port F Registers
Name
Abbreviation
R/W
Initial Value
Address*
1
Port F data direction register
PFDDR
W
H'80/H'00*
2
H'FE3E
Port F data register
PFDR
R/W
H'00
H'FF0E
Port F register
PORTF
R
Undefined
H'FFBE
Notes: *1 Lower 16 bits of the address.
*2 Initial value depends on the mode. Initialized to H'80 in modes 4 to 6, and to H'00 in
mode 7.
(1) Port F Data Direction Register (PFDDR)
7
PF7DDR
1
W
0
W
6
PF6DDR
0
W
0
W
5
PF5DDR
0
W
0
W
4
PF4DDR
0
W
0
W
3
PF3DDR
0
W
0
W
0
PF0DDR
0
W
0
W
2
PF2DDR
0
W
0
W
1
PF1DDR
0
W
0
W
Bit
:
Modes 4 to 6 :
Initial value
:
R/W
:
Mode 7
:
Initial value
:
R/W
:
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read..
PFDDR is initialized to H'80 (modes 4 to 6) or H'00 (mode 7) by a power-on reset and in hardware
standby mode. It retains its previous state after a manual reset and in software standby mode. The
OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or
become high-impedance when a transition is made to software standby mode.
(a)Modes 4 to 6
Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specification in PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (
AS, RD, HWR, and LWR).
Pins PF2 to PF0 are made bus control input/output pins (
WAIT, BACK, and BREQ) by bus
controller settings. Otherwise, setting a PFDDR bit to 1 makes the corresponding pin an
output port, while clearing the bit to 0 makes the pin an input port.