
79
Address bus
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1) (3) Reset exception handling vector address (for a power-on reset, (1) = H'000000,
(3) = H'000002; for a manual reset, (1) = H'000004, (3) = H'000006)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
RES, MRES
(1)
(5)
High
(2)
(4)
(3)
(6)
RD
HWR, LWR
D15 to D0
*
Note: * Three program wait states are inserted.
**
Figure 4-3 Reset Sequence (Mode 4)
4.2.4
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.5
State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to
H'FF, and all modules except the DMAC and DTC enter module stop mode. Consequently, on-
chip supporting module registers cannot be read or written to. Register reading and writing is
enabled when module stop mode is exited.