
xxiv
Table 9-23
Port F Pin Functions ............................................................................................ 333
Table 9-24
Port G Registers ................................................................................................... 336
Table 9-25
Port G Pin Functions............................................................................................ 338
Table 10-1
TPU Functions ..................................................................................................... 343
Table 10-2
TPU Pins .............................................................................................................. 346
Table 10-3
TPU Registers ...................................................................................................... 347
Table 10-4
TPU Clock Sources.............................................................................................. 350
Table 10-5
Register Combinations in Buffer Operation ........................................................ 381
Table 10-6
PWM Output Registers and Output Pins ............................................................. 386
Table 10-7
Phase Counting Mode Clock Input Pins .............................................................. 390
Table 10-8
Up/Down-Count Conditions in Phase Counting Mode 1 .................................... 391
Table 10-9
Up/Down-Count Conditions in Phase Counting Mode 2 .................................... 392
Table 10-10
Up/Down-Count Conditions in Phase Counting Mode 3 .................................... 393
Table 10-11
Up/Down-Count Conditions in Phase Counting Mode 4 .................................... 394
Table 10-12
Interrupt Sources and DMA Controller (DMAC)
and Data Transfer (DTC) Activation ................................................................... 395
Table 11-1
WDT Registers..................................................................................................... 417
Table 12-1
SCI Pins................................................................................................................ 435
Table 12-2
SCI Registers........................................................................................................ 436
Table 12-3
BRR Settings for Various Bit Rates (Asynchronous Mode)................................ 450
Table 12-4
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ................... 453
Table 12-5
Maximum Bit Rate for Each Frequency (Asynchronous Mode) ......................... 455
Table 12-6
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ............... 456
Table 12-7
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ... 456
Table 12-8
SMR Settings and Serial Transfer Format Selection ........................................... 465
Table 12-9
SMR and SCR Settings and SCI Clock Source Selection ................................... 465
Table 12-10
SMR0, SCR0, SEMR0 Settings and SCI Clock Source Selection (SCI0 Only) .. 466
Table 12-11
Serial Transfer Formats (Asynchronous Mode) .................................................. 469
Table 12-12
Receive Errors and Conditions for Occurrence ................................................... 478
Table 12-13
SCI Interrupt Sources........................................................................................... 496
Table 12-14
State of SSR Status Flags and Transfer of Receive Data..................................... 497
Table 13-1
Pin Configuration ................................................................................................. 509
Table 13-2
D/A Converter Registers...................................................................................... 509
Table 14-1
RAM Register ...................................................................................................... 514
Table 15-1
ROM Register ...................................................................................................... 518
Table 15-2
Operating Modes and ROM Area (F-ZTAT version and Mask ROM version) .. 519
Table 15-3
Differences between Boot Mode and User Program Mode ................................. 526
Table 15-4
Pin Configuration ................................................................................................. 528
Table 15-5
Register Configuration ......................................................................................... 529
Table 15-6
Flash Memory Erase Blocks ................................................................................ 535
Table 15-7
Flash Memory Area Divisions ............................................................................. 536
Table 15-8
Setting On-Board Programming Modes .............................................................. 538