
332
(b)Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the output pin. Clearing the bit to 0 makes the pin an input port.
(2) Port F Data Register (PFDR)
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
0
PF0DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
Bit
:
Initial value
:
R/W
:
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port F Register (PORTF)
7
PF7
—*
R
6
PF6
—*
R
5
PF5
—*
R
4
PF4
—*
R
3
PF3
—*
R
0
PF0
—*
R
2
PF2
—*
R
1
PF1
—*
R
Bit
:
Initial value :
R/W
:
Note: * Determined by the state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its previous state after a manual reset
and in software standby mode.
9.12.3
Pin Functions
Port F pins also function as external interrupt input pins (
IRQ2 and IRQ3), bus control signal I/O
pins (
AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the system clock () output pin. The
pin functions differ between modes 4 to 6 and mode 7. Port F pin functions are shown in table 9-
23.