
281
(1) Port 3 Data Direction Register (P3DDR)
7
—
Undefined
—
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
0
P30DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
Bit
:
Initial value :
R/W
:
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. Bit 7 is
reserved; this bit cannot be modified and will return an undefined value if read.
Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. As the SCI is initialized by a
manual reset, the pin states in this case are determined by the P3DDR and P3DR specifications.
(2) Port 3 Data Register (P3DR)
7
—
Undefined
—
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
0
P30DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
Bit
:
Initial value :
R/W
:
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P36 to P30).
Bit 7 is reserved; this bit cannot be modified and will return an undefined value if read.
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(3) Port 3 Register (PORT3)
7
—
Undefined
—
6
P36
—*
R
5
P35
—*
R
4
P34
—*
R
3
P33
—*
R
0
P30
—*
R
2
P32
—*
R
1
P31
—*
R
Bit
:
Initial value :
R/W
:
Note: * Determined by the state of pins P36 to P30.