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9.2.2
Register Configuration
Table 9-2 shows the port 1 register configuration.
Table 9-2
Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Port 1 data register
P1DR
R/W
H'00
H'FF00
Port 1 register
PORT1
R
Undefined
H'FFB0
Note: * Lower 16 bits of the address.
(1) Port 1 Data Direction Register (P1DDR)
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
Bit
:
Initial value :
R/W
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
P1DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode. As the TPU is initialized by a
manual reset, the pin states in this case are determined by the P1DDR and P1DR specifications.
The OPE bit in SBYCR is used to select whether the address output pins retain their output state
or become high-impedance when a transition is made to software standby mode.
(a)Modes 4, 5, and 6
If address output is enabled by the setting of bits AE3 to AE0 in PFCR, pins P13 to P10 are
address outputs. Pins P17 to P14, and pins P13 to P10 when address output is disabled, are
output ports when the corresponding P1DDR bits are set to 1, and input ports when the
corresponding P1DDR bits are cleared to 0.
(b)Mode 7
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output port, while clearing the
bit to 0 makes the pin an input port.