
743
TCR0—Timer Control Register 0
H'FF10
TPU0
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Bit
Initial value
R/W
:
Counter Clear 2 to 0
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing
synchronous clearing/synchronous operation *1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture *2
TCNT cleared by TGRD compare match/input capture *2
TCNT cleared by counter clearing for another channel performing
synchronous clearing/synchronous operation *1
0
1
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer
register setting has priority, and compare match/input capture does not occur.
0
1
0
1
0
1
0
1
0
1
0
1
Clock Edge 1 and 0
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Time Prescaler 2 to 0
Internal clock: counts on /1
Internal clock: counts on /4
Internal clock: counts on /16
Internal clock: counts on /64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
0
1
0
1
0
1
0
1
0
1
0
1
0
1