
List of Items Revised or Added for This Version
Section
Title
Page
Revisions
(See Manual for Details)
Section 1
Overview
1.1
Overview
2
Table 1-1 Overview
Description of DMA Controller
(DMAC) amended.
1.2
Internal Block Diagrams 5
Figure 1-1 H8S/2214 Internal Block
Diagram amended.
1.3.1
Pin Arrangements
6
Figure 1-2 H8S/2214 Pin
Arrangement (TFP-100B, TFP-
100G: Top View) amended.
1.3.2
Pin Functions in Each
Operating Mode
9
Table 1-2 Pin Functions in Each
Operating Mode
Mode of pin Nos. 34 and 35 revised
from 4 to 7.
1.3.3
Pin Functions
14
Table 1-3 Pin Functions.
Description of DMA Controller
(DMAC) amended.
Section 7
DMA
7.1.1
Features
163
Description of Short Address Mode
amended.
Controller
7.1.2
Block Diagram
164
Figure 7-1 Block Diagram of DMAC
amended.
7.1.3
Overview of Functions
165
Table 7-1 Overview of DMAC
Functions (Short Address Mode)
Description of Single Address Mode
deleted.
7.1.4
Pin Configuration
167
Description of Pin Configuration
amended.
Table 7-3 DMAC Pins amended.
7.2.4
DMA Control Register
(DMACR)
173
Description of Bit 4: Data Transfer
Direction (DTDIR) amended, and
Table amended.
7.2.5
DMA Band Control
Register (DMABCR)
176
DMABCRH of Bits 13 and 12
changed to "—."
Bits 13 and 12—Reserved bits.
Description of 12 and 13 grouped
together.
7.3.5
DMA Band Control
Register (DMABCR)
189
Revised as follows:
Bits 10 and 8—Reserved (DTA1A,
DTA0A): Reserved bits in full
address mode. Read and write
possible.