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requested, it will not be possible to clear the CPU interrupt source, DMAC, or DTC activation
source. Interrupts should therefore be disabled before setting module stop mode.
Writing to MSTPCR: MSTPCR should be written to only by the CPU.
17.6
Software Standby Mode
17.6.1
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and
oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states
of on-chip supporting module, and of the I/O ports, are retained. The address bus and bus control
signals are placed in the high-impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
17.6.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins
IRQ0 to IRQ7), or by
means of the
RES pin, MRES pin or STBY pin.
Clearing with an Interrupt: When an NMI or IRQ0 to IRQ7 interrupt request signal is input,
clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable
clocks are supplied to the entire H8S/2214 chip, software standby mode is cleared, and interrupt
exception handling is started.
When software standby mode is cleared with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that an interrupt of higher priority than interrupts IRQ0 to IRQ7 is not
generated. Software standby mode cannot be cleared if the interrupt has been masked by the CPU
side or has been designated as a DTC activation source.
Clearing with the
RES Pin and MRES Pin: When the RES pin and MRES pin are driven low,
clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the
entire H8S/2214 chip. Note that the
RES pin and MRES pin must be held low until clock
oscillation stabilizes. When the
RES pin and MRES pin go high, the CPU begins reset exception
handling.
Clearing with the
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
standby mode.