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17.2.2
System Clock Control Register (SCKCR)
7
PSTOP
0
R/W
6
—
0
R/W
5
—
0
—
4
—
0
—
3
—
0
R/W
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
:
Initial value :
R/W
:
SCKCR is an 8-bit readable/writable register that performs clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7— Clock Output Disable (PSTOP): Controls output.
Description
Bit 7
High–Speed Mode
Software Standby
Hardware
PSTOP
Medium-Speed Mode
Sleep Mode
Mode, Watch
Standby Mode
0
output (initial value)
output
Fixed high
High impedance
1
Fixed high
High impedance
Bits 6 and 3—Reserved: These bits can be read or written to, but should only be written with 0.
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
Bus master is in high-speed mode
(Initial value)
1
Medium-speed clock is /2
1
0
Medium-speed clock is /4
1
Medium-speed clock is /8
1
0
Medium-speed clock is /16
1
Medium-speed clock is /32
1—
—