
579
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
used in high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
Bus master is in high-speed mode
(Initial value)
1
Medium-speed clock is /2
1
0
Medium-speed clock is /4
1
Medium-speed clock is /8
1
0
Medium-speed clock is /16
1
Medium-speed clock is /32
1—
—
16.2.2
Low-Power Control Register (LPWRCR)
7
—
0
R/W
6
—
0
R/W
5
—
0
R/W
4
—
0
R/W
3
RFCUT
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit
:
Initial value :
R/W
:
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bits 7 to 4—Reserved: These bits can be read or written to, but only 0 should be written.
Bit 3—Built-in Feedback Resistor Control (RFCUT): Selects whether the oscillator’s built-in
feedback resistor and duty adjustment circuit are used with external clock input. Do not access this
bit when a crystal oscillator is used.
After this bit is set when using external clock input, a transition should intially be made to
software standby mode, watch mode, or subactive mode. Switching between use and non-use of
the oscillator’s built-in feedback resistor and duty adjustment circuit is performed when the
transition is made to software standby mode, watch mode, or subactive mode.