
748
TSR0—Timer Status Register 0
H'FF15
TPU0
7
—
1
—
6
—
1
—
5
—
0
—
4
TCFV
0
R/(W)*
3
TGFD
0
R/(W)*
0
TGFA
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
Bit
Initial value
R/W
Note: * Can only be written with 0 for flag clearing.
:
Overflow Flag
0
1
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Input Capture/Output Compare Flag A
0
1
[Clearing conditions]
When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1
When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
When TCNT = TGRA while TGRA is functioning as output compare register
When TCNT value is transferred to TGRA by input capture signal while TGRA
is functioning as input capture register
Input Capture/Output Compare Flag B
0
1
[Clearing conditions]
When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
When TCNT = TGRB while TGRB is functioning as output compare register
When TCNT value is transferred to TGRB by input capture signal while TGRB
is functioning as input capture register
Input Capture/Output Compare Flag C
0
1
[Clearing conditions]
When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
When TCNT = TGRC while TGRC is functioning as output compare register
When TCNT value is transferred to TGRC by input capture signal while TGRC
is functioning as input capture register
Input Capture/Output Compare Flag D
0
1
[Clearing conditions]
When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
When TCNT = TGRD while TGRD is functioning as output compare register
When TCNT value is transferred to TGRD by input capture signal while TGRD
is functioning as input capture register