
547
Start
Programming end
Return
Set SWE1 bit in FLMCR1
Wait: tSSWE
n = 1
m = 0
Subroutine call
Note *6: Write Pulse Width
Start of subroutine
Set PSU1 bit in FLMCR1
Enable WDT
Set P1 bit in FLMCR1
Wait: tSPSU
Clear P1 bit in FLMCR1
Wait: tSP10 or tSP200
Clear PSU1 bit in FLMCR1
Wait: tCP
Disable WDT
Wait: tCPSU
Subroutine: Write Pulse
No
Subroutine call
See Note *6 for pulse width
No
Yes
Wait: tSPV
Wait: tSPVR
*2
*4
*1
*5
*1
Write Pulse (tSP10)
Set PV1 bit in FLMCR1
Perform H'FF dummy-write to verify address
Read verify data
Write data =
verify data?
6
≥ n?
6
≥ n?
*4
*3
Compute additional-programming data
Wait: tCSWE
m = 1
128 byte data
verify complete?
m = 0?
Increment
address
Programming failure
Wait: tCSWE
Clear SWE1 bit in FLMCR1
n
≥ 1000?
Reprogram Data
(X')
00
0
01
1
10
1
11
1
Verify Data
(V)
Additional-Programming
Data (Y)
Comments
Additional programming executed
Additional programming not executed
Successively write 128-byte data from
reprogram data area in RAM to flash memory
Write Pulse (tSP30 or tSP200)
RAM
Program data storage area
(128 bytes)
Reprogram data storage area
(128 bytes)
Additional program data
storage area (128 bytes)
Store 128 bytes program data in program
data area and reprogram data area
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
.
998
999
1000
Write Time (tSP30/tSP200) s
tSP30
tSP200
.
tSP200
Original Data
(D)
Verify Data
(V)
01
0
10
0
Reprogram Data
(X)
Comments
Programming complete.
Programming is incomplete;
reprogramming should be performed.
Reprogram Data Computation Table
01
1
—
11
1
Left in the erased state.
Additional-Programming Data Computation Table
Transfer additional-programming data
to additional-programming data area
Compute reprogram data
Clear PV1 bit in FLMCR1
Wait: tCPV
Transfer reprogram data to reprogram
data area
Successively write 128-byte data
from additional-programming data area
in RAM to flash memory
n
← n + 1
Note: Use a tSP10 write pulse for additional programming.
Notes: *1 Transfer data in byte units. The lower eight bits of the start
address to which data is written must be H'00 or H'80.
Transfer 128-byte data even when writing fewer than 128 bytes.
In this case, Set H'FF in unused addresses.
*2 Read verify data in longword form (32 bits).
*3 Even for bits to which data is already written, an additional write
should be performed if their verify result is NG.
*4 A 128-byte area for storing program data, a 128-byte area for
storing reprogram data, and a 128-byte area for storing additional
program data must be provided in RAM. The reprogram and
additional program data contents are modified as programming
proceeds.
*5 A write pulse of tSP30 or tSP200 is applied according to the
progress of the programming operation. See Note 6 for the pulse
widths. When writing of the additional program data is executed,
a tSP10 write pulse should be applied. Reprogram data X' means
reprogram data when the pulse is applied.
Data writes must be performed
in the memory-erased state.
Do not write additional data to
an address to which data is
already written.
Figure 15-14 Program/Program-Verify Flowchart