
xi
15.9.1 Program Mode....................................................................................................... 545
15.9.2 Program-Verify Mode ........................................................................................... 546
15.9.3 Erase Mode............................................................................................................ 548
15.9.4 Erase-Verify Mode................................................................................................ 548
15.10 Protection............................................................................................................................ 550
15.10.1 Hardware Protection.............................................................................................. 550
15.10.2 Software Protection ............................................................................................... 551
15.10.3 Error Protection ..................................................................................................... 552
15.11 Flash Memory Emulation in RAM..................................................................................... 554
15.12 Interrupt Handling when Programming/Erasing Flash Memory........................................ 556
15.13 Flash Memory Programmer Mode ..................................................................................... 556
15.13.1 Socket Adapter Pin Correspondence Diagram...................................................... 557
15.13.2 Programmer Mode Operation................................................................................ 559
15.13.3 Memory Read Mode.............................................................................................. 560
15.13.4 Auto-Program Mode.............................................................................................. 563
15.13.5 Auto-Erase Mode .................................................................................................. 565
15.13.6 Status Read Mode.................................................................................................. 567
15.13.7 Status Polling ........................................................................................................ 568
15.13.8 Programmer Mode Transition Time...................................................................... 568
15.13.9 Notes on Memory Programming........................................................................... 569
15.14 Flash Memory and Power-Down States ............................................................................. 570
15.14.1 Note on Power-Down States ................................................................................. 570
15.15 Flash Memory Programming and Erasing Precautions...................................................... 571
15.16 Note on Switching from F-ZTAT Version to Mask ROM Version ................................... 576
Section 16 Clock Pulse Generator ................................................................................... 577
16.1
Overview ............................................................................................................................ 577
16.1.1 Block Diagram ...................................................................................................... 577
16.1.2 Register Configuration.......................................................................................... 578
16.2
Register Descriptions.......................................................................................................... 578
16.2.1 System Clock Control Register (SCKCR) ............................................................ 578
16.2.2 Low-Power Control Register (LPWRCR) ............................................................ 579
16.3
System Clock Oscillator ..................................................................................................... 581
16.3.1 Connecting a Crystal Resonator............................................................................ 581
16.3.2 External Clock Input ............................................................................................. 583
16.4
Duty Adjustment Circuit .................................................................................................... 586
16.5
Medium-Speed Clock Divider............................................................................................ 586
16.6
Bus Master Clock Selection Circuit ................................................................................... 586
16.7
Note on Crystal Resonator.................................................................................................. 586
Section 17 Power-Down Modes ....................................................................................... 587
17.1
Overview ............................................................................................................................ 587
17.1.1 Register Configuration .......................................................................................... 590