
586
16.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock ().
16.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
16.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock () or one of the medium-speed
clocks (/2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
16.7
Note on Crystal Resonator
Since various characteristics related to the crystal resonator are closely linked to the user’s board
design, thorough evaluation is necessary on the user’s part, for both the mask versions, and F-
ZTAT versions, using the resonator connection examples shown in this section as a guide. As the
resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting
circuit, the ratings should be determined in consultation with the resonator manufacturer. The
design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator
pin.