
446
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
Description
0
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
1
[Setting conditions]
(Initial value)
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
Description
0
[Clearing conditions]
(Initial value)
When 0 is written to RDRF after reading RDRF = 1
When the DTC is activated by an RXI interrupt and reads data from RDR
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note:
RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
(Initial value)*
1
When 0 is written to ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1*
2
Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
*2 The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.