
536
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3
RAMS
Description
0
Emulation not selected
(Initial value)
Program/erase-protection of all flash memory blocks is disabled
1
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bit 2—Reserved: Only 0 should be written to this bit.
Bits 1 and 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the
flash memory area to be overlapped with RAM. (See table 15-7.)
Table 15-7 Flash Memory Area Divisions
Addresses
Block Name
RAMS
RAM1RAM0
H'FFD000–H'FFD3FF
RAM area 1 kbyte
0
**
H'000000–H'0003FF
EB0 (1 kbyte)
1
0
H'000400–H'0007FF
EB1 (1 kbyte)
1
0
1
H'000800–H'000BFF
EB2 (1 kbyte)
1
0
H'000C00–H'000FFF
EB3 (1 kbyte)
1
*: Don’t care
15.7.6
Serial Control Register X (SCRX)
Bit:
7
6
5
4
3
2
1
0
—
FLSHE
—
Initial value:
0
R/W:
R/W
SCRX is an 8-bit readable/writable register that performs register access control, and on-chip flash
memory control (including the F-ZTAT version).
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.