
iv
6.3
Overview of Bus Control.................................................................................................... 126
6.3.1
Area Divisions....................................................................................................... 126
6.3.2
Bus Specifications ................................................................................................. 127
6.3.3
Memory Interfaces ................................................................................................ 128
6.3.4
Interface Specifications for Each Area.................................................................. 129
6.3.5
Chip Select Signals................................................................................................ 130
6.4
Basic Bus Interface............................................................................................................. 131
6.4.1
Overview ............................................................................................................... 131
6.4.2
Data Size and Data Alignment.............................................................................. 131
6.4.3
Valid Strobes........................................................................................................ 133
6.4.4
Basic Timing ......................................................................................................... 134
6.4.5
Wait Control.......................................................................................................... 142
6.5
Burst ROM Interface .......................................................................................................... 144
6.5.1
Overview ............................................................................................................... 144
6.5.2
Basic Timing ......................................................................................................... 144
6.5.3
Wait Control.......................................................................................................... 146
6.6
Idle Cycle............................................................................................................................ 147
6.6.1
Operation ............................................................................................................... 147
6.6.2
Pin States in Idle Cycle ......................................................................................... 150
6.7
Bus Release ........................................................................................................................ 151
6.7.1
Overview ............................................................................................................... 151
6.7.2
Operation ............................................................................................................... 151
6.7.3
Pin States in External Bus Released State ............................................................ 152
6.7.4
Transition Timing.................................................................................................. 153
6.7.5
Usage Note ............................................................................................................ 154
6.8
Bus Arbitration ................................................................................................................... 154
6.8.1
Overview ............................................................................................................... 154
6.8.2
Operation ............................................................................................................... 154
6.8.3
Bus Transfer Timing ............................................................................................. 155
6.8.4
External Bus Release Usage Note ......................................................................... 155
6.9
Resets and the Bus Controller ............................................................................................ 156
6.10
External Module Expansion Function................................................................................ 156
6.10.1 Overview ............................................................................................................... 156
6.10.2 Pin Configuration .................................................................................................. 157
6.10.3 Register Configuration .......................................................................................... 157
6.11
Register Descriptions.......................................................................................................... 158
6.11.1 Interrupt Request Input Pin Select Register 0 (IPINSEL0) .................................. 158
6.11.2 External Module Connection Output Pin Select Register (OPINSEL)................. 160
6.11.3 Module Stop Control Register B (MSTPCRB)..................................................... 161
6.12
Basic Timing ...................................................................................................................... 162
Section 7
DMA Controller............................................................................................... 163
7.1
Overview ............................................................................................................................ 163