
722
DTCER—DTC Enable Registers
H'FE16 to H'FE1E
DTC
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
Bit
Initial value
R/W
:
DTC Activation Enable
0
1
DTC activation by this interrupt is disabled
[Clearing conditions]
When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
DTVECR—DTC Vector Register
H'FE1F
DTC
7
SWDTE
0
R/(W)*1
6
DTVEC6
0
R/W*2
5
DTVEC5
0
R/W*2
4
DTVEC4
0
R/W*2
3
DTVEC3
0
R/W*2
0
DTVEC0
0
R/W*2
2
DTVEC2
0
R/W*2
1
DTVEC1
0
R/W*2
Notes: *1
Only 1 can be written to the SWDTE bit.
*2
Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Bit
Initial value
R/W
:
DTC Software Activation Enable
Sets vector number for DTC software activation
0
1
DTC software activation is disabled
[Clearing conditions]
When the DISEL bit is 0 and the specified number of transfers have not ended
When 0 is written to the DISEL bit after a software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU
DTC software activation is enabled
[Holding conditions]
When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation