
368
Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
Description
0
TCNTn count operation is stopped
(Initial value)
1
TCNTn performs count operation
(n = 2 to 0)
Note:
If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
10.2.9
Timer Synchro Register (TSYR)
7
—
0
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
SYNC0
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
Bit
Initial value
R/W
:
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channels 0 to 2 TCNT counters. A channel performs synchronous operation
when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 3—Reserved: Should always be written with 0.
Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*
1, and
synchronous clearing through counter clearing on another channel*
2 are possible.
Notes: *1 To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
*2 To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.