
320
9.10.2
Register Configuration
Table 9-18 shows the port D register configuration.
Table 9-18 Port D Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port D data direction register
PDDDR
W
H'00
H'FE3C
Port D data register
PDDR
R/W
H'00
H'FF0C
Port D register
PORTD
R
Undefined
H'FFBC
Port D MOS pull-up control register
PDPCR
R/W
H'00
H'FE43
Note: * Lower 16 bits of the address.
(1) Port D Data Direction Register (PDDDR)
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
3
PD3DDR
0
W
0
PD0DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
Bit
:
Initial value :
R/W
:
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
previous state after a manual reset and in software standby mode.
(a)Modes 4 to 6
The input/output direction settings in PDDDR are ignored, and port D pins automatically
function as data input/output pins.
(b)Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.