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11.3
Operation
11.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/
IT and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally.
In this way, TCNT will not overflow while the system is operating normally, but if TCNT is not
rewritten and overflows because of a system crash or other error, in the case of WDT, if the RSTE
bit in RSTCSR is set to 1 beforehand, a signal is generated that effects an internal chip reset.
Either a power-on reset or a manual reset can be selected with the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states. This is illustrated in figure 11-4.
If a reset caused by an input signal from the
RES pin and a reset caused by WDT overflow occur
simultaneously, the
RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
TCNT value
H'00
Time
H'FF
WT/IT = 1
TME = 1
H'00 written
to TCNT
WT/IT = 1
TME = 1
H'00 written
to TCNT
518 states (WDT0)
Internal reset signal*
Overflow
Internal reset
generated
WOVF = 1
WT/IT: Timer mode select bit
TME:
Timer enable bit
Note: *
With WDT, the internal reset signal is generated only when the RSTE bit is set to 1.
Figure 11-4 Operation in Watchdog Timer Mode