
94
Figure 5-3 shows the timing of setting IRQnF.
IRQn
input pin
IRQnF
Figure 5-3 Timing of Setting IRQnF
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request
flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting,
only the necessary flags should be referenced.
EXIRQ7 to EXIRQ0 Interrupts: Interrupts EXIRQ7 to EXIRQ0 are for use by external
expansion modules. An interrupt is requested by a low-level input signal at one of pins EXIRQ7
to EXIRQ0.
5.3.2
Internal Interrupts
There are 31 sources for internal interrupts from on-chip supporting modules.
For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
The interrupt priority level can be set by means of IPR.
The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request.
When the DMAC and DTC is activated by an interrupt, the interrupt control mode and
interrupt mask bits are not affected.
5.3.3
Interrupt Exception Handling Vector Table
Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.