
734
WCRL—Wait Control Register L
H'FED3
Bus Controller
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
0
W00
1
R/W
2
W10
1
R/W
1
W01
1
R/W
Bit
Initial value
R/W
:
Area 3 Wait Control 1 and 0
Area 0 Wait Control 1 and 0
Program wait not inserted in area 0 external space access
1 program wait state inserted in area 0 external space access
2 program wait states inserted in area 0 external space access
3 program wait states inserted in area 0 external space access
0
1
0
1
0
1
Program wait not inserted in area 1 external space access
1 program wait state inserted in area 1 external space access
2 program wait states inserted in area 1 external space access
3 program wait states inserted in area 1 external space access
0
1
0
1
0
1
Program wait not inserted in area 2 external space access
1 program wait state inserted in area 2 external space access
2 program wait states inserted in area 2 external space access
3 program wait states inserted in area 2 external space access
0
1
0
1
0
1
Program wait not inserted in area 3 external space access
1 program wait state inserted in area 3 external space access
2 program wait states inserted in area 3 external space access
3 program wait states inserted in area 3 external space access
0
1
0
1
0
1
Area 1 Wait Control 1 and 0
Area 2 Wait Control 1 and 0