
763
DMACR0A—DMA Control Register 0A
DMACR0B—DMA Control Register 0A
DMACR1A—DMA Control Register 1A
DMACR1B—DMA Control Register 1B
H'FF62
H'FF63
H'FF64
H'FF65
DMAC
7
DTSZ
0
R/W
6
DTID
0
R/W
5
RPE
0
R/W
4
DTDIR
0
R/W
3
DTF3
0
R/W
0
DTF0
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
Byte size transfer
Word size transfer
0
1
0
Data transfer size
MAR incremented after data transfer
(1) When DTSZ=0, MAR + 1 after transfer.
(2) When DTSZ=1, MAR + 2 after transfer.
MAR decremented after data transfer
(1) When DTSZ=0, MAR – 1 after transfer.
(2) When DTSZ=1, MAR – 2 after transfer.
1
Data transfer increment/decrement
Repeat enable
Data transfer direction
Data transfer factor
Channel A
Channel B
Sequential mode transfer (no transfer end interrrupt).
Sequential mode transfer (with transfer end interrupt).
Transfer in repeat mode (no transfer end interrupt).
Transfer in idle mode (with transfer end interrupt).
0
1
0
DTIE
DMABCR
RPE
0
1
Transfer from MAR as source address to IOAR as destination address.
Transfer from IOAR as source address to MAR as destination address.
Transfer from MAR as source address with DACK pin as write strobe.
Transfer with DACK pin as read strobe to MAR as destination address.
0
1
0
DTDIR
DMABCR
SAE
0
1
—
0
1
0
1
Starts on SCI channel 0 transmit end interrupt
Starts on SCI channel 0 receive end interrupt
Starts on SCI channel 1 transmit end interrupt
Starts on SCI channel 1 receive end interrupt
Starts on TPU channel 0 compare match/input capture A interrupt
Starts on TPU channel 1 compare match/input capture A interrupt
Starts on TPU channel 2 compare match/input capture A interrupt
—
0
1
0
1
0
1
0
1
0
1
—
0
1
0
1
0
1
—
Starts on falling edge of input at DREQ pin
Starts on LOW level input at DREQ pin
Starts on SCI channel 0 transmit end interrupt
Starts on SCI channel 0 receive end interrupt
Starts on SCI channel 1 transmit end interrupt
Starts on SCI channel 1 receive end interrupt
Starts on TPU channel 0 compare match/input capture A interrupt
Starts on TPU channel 1 compare match/input capture A interrupt
Starts on TPU channel 2 compare match/input capture A interrupt
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
0
1
0
1
0
1
Note: * Detect the first transfer after transfers have been enabled as a LOW level signal.
Bit
DMACR
Initial value
R/W
: