
301
(4) Port A MOS Pull-Up Control Register (PAPCR)
7
—
Undefined
—
6
—
Undefined
—
5
—
Undefined
—
4
—
Undefined
—
3
PA3PCR
0
R/W
0
PA0PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
Bit
:
Initial value :
R/W
:
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on a bit-by-bit basis.
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAPCR is valid for port input and SCI input pins. When a PADDR bit is cleared to 0 (input port
setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the
corresponding pin.
PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
(5) Port A Open-Drain Control Register (PAODR)
7
—
Undefined
—
6
—
Undefined
—
5
—
Undefined
—
4
—
Undefined
—
3
PA3ODR
0
R/W
0
PA0ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
Bit
:
Initial value :
R/W
:
PAODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port A
pin (PA3 to PA0).
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAODR is valid for port output and SCI output pins.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
9.7.3
Pin Functions
Port A pins also function as SCI2 I/O pins (TxD2, RxD2, and SCK2) and address output pins
(A19 to A16). Port A pin functions are shown in table 9-11.