
356
Bit 7
Bit 6
Bit 5
Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
0
000
1
0
1
0
1
TGR0D is
output
compare
register*
1
Output disabled
Initial output is 0
output
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
0
Output disabled
1
Initial output is 1
0 output at compare match
10
output
1 output at compare match
1
Toggle output at compare
match
100
1
0
1
*
TGR0D is
input
capture
register*
1
Capture input
source is
TIOCD0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
**
Setting prohibited
*: Don’t care
Note:
*1 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 7
Bit 6
Bit 5
Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
1
000
1
0
1
0
1
TGR1B is
output
compare
register
Output disabled
Initial output is 0
output
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
0
Output disabled
1
Initial output is 1
0 output at compare match
10
output
1 output at compare match
1
Toggle output at compare
match
1
0
1
0
1
*
TGR1B is
input
capture
register
Capture input
source is
TIOCB1 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
**
Setting prohibited
*: Don’t care