
595
Bus master clock
,
supporting module
clock
Internal address
bus
Internal write signal
Medium-speed mode
SBYCR
Figure 17-2 Medium-Speed Mode Transition and Clearance Timing
17.4
Sleep Mode
17.4.1
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
17.4.2
Clearing Sleep Mode
Sleep mode is cleared by all interrupts, or with the
RES pin, MRES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and
interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or
if interrupts other than NMI have been masked by the CPU.
Clearing with the
RES Pin and MRES Pin: When the RES pin and MRES pin is driven low, the
reset state is entered. When the
RES pin and MRES pin is driven high after the prescribed reset
input period, the CPU begins reset exception handling.
Clearing with the
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
standby mode.