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PRELIMINARY
XRT79L71
150
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Once the user executes these two steps, then the Transmit DS3/E3 Framer block will automatically set the
FEBE bit-fields within each outbound DS3 frame to the value written into Bits 7 through 5 (TxFEBEDat[2:0])
within the Transmit DS3 M-Bit Mask Register.
NOTE: In this configuration, the value of the FEBE bit-fields that are being generated by the Transmit DS3/E3 Framer block
do not reflect the health of the DS3 signal that is being received by the corresponding Near-End Receive DS3/E3
Framer block.
4.2.5.6.2
Automatic Transmission of the FEBE Indicator
If the Forced Transmission of the FEBE Indicator feature (as described above) is not used, then the Transmit
DS3 Framer block will be configured to automatically set the FEBE bit-fields, within the outbound DS3 data
stream, based upon occurrences as detected by the corresponding Receive DS3/E3 Framer block.
If the companion Receive DS3/E3 Framer block does not detect any F, M or CP-bit errors, then the Transmit
DS3/E3 Framer block will respond by setting all of the FEBE bit-fields within each outbound DS3 frame to "1".
Hence, in this case, the FEBE value, for each outbound DS3 data stream will be set to "1, 1, 1". According to
Bellcore GR-499-CORE, the FEBE value of "1, 1, 1" represents an un-erred condition.
Conversely, if at a given instant, the companion Receive DS3/E3 Framer block does detect any F, M or CP-bit
errors, then the Transmit DS3/E3 Framer block will respond by setting the FEBE value within its next outbound
DS3 frame to a value other than "1, 1, 1". According to Bellcore GR-499-CORE, the FEBE value of something
other than "1, 1, 1" represents an erred condition. In general, the Transmit DS3/E3 Framer block will transmit
an erred FEBE indicator each time that the corresponding Near-End Receive DS3/E3 Framer block receives
an erred DS3 frame.
NOTE: The Automatic Transmission of FEBE Indicator feature is enabled by setting Bit 4 (FEBE Register Enable) within the
Transmit DS3 M-Bit Mask Register to "0", as illustrated below.
4.2.5.7
Setting the Transmit DS3 Framer Block Timing Reference
When designing your system, a decision must be made as to whether the system is going to be configured to
operate in either the Local-Timing Mode (e.g., where the timing source for the Transmit [or outbound] Direction
traffic is derived from a "local" [or in-system] clock source) or in the Loop-Timing Mode (e.g., where the timing
source for the Transmit [or outbound] Direction traffic is derived from the "remote terminal equipment's" clock
source. The XRT79L71 can be configured to support either of these applications.
In all, the XRT79L71 supports the following three (3) different "Timing Reference" Modes.
Transmit DS3 M-Bit Mask Register (Address = 0x1135)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFEBEDat[2:0]
FEBE
Register
Enable
Tx P-Bit
Error
TxM_Bit_Mask[2:0]
R/W
X
1
0
Transmit DS3 M-Bit Mask Register (Address = 0x1135)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFEBEDat[2:0]
FEBE
Register
Enable
Tx P-Bit
Error
TxM_Bit_Mask[2:0]
R/W
0