
XRT79L71
PRELIMINARY
445
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
This can be accomplished by setting Bits 1 and 0 (TimRefSel[1:0]) within the "Framer Operating Mode"
Register to "[1, X]" as depicted below.
6.2.1.4
Mode 4 - Nibble-Parallel/Loop-Timing Mode Operation of the Transmit Payload Data Input
Interface Block
If the XRT79L71 is configured to operate in "Mode 4" then all of the following is true.
The XRT79L71 will be configured to operate in the "Loop-Timing" Mode. In other words, the Transmit
Section of the XRT79L71 will use the Recovered Clock signal (from the Receive E3 LIU Block) as its timing
source.
In this mode, the XRT79L71 will use the LIU Recovered Clock signal to derive the "TxNibClk" signal.
For E3 Applications, the "TxNibClk" frequency is exactly one-fourth of the LIU Recovered Clock signal (or
8.592MHz).
Since the XRT79L71 is configured to operate in the "Nibble-Parallel" Mode, it will sample and latch the data,
being applied to the "TxNib[3:0]" input pins upon the third rising edge of the "RxOutClk" output clock signal,
following a given rising edge of the "TxNibClk" output clock signal.
The XRT79L71 will pulse the "TxNibFrame" output pin "high" for one nibble-period coincident to whenever
the Transmit Payload Data Input Interface is processing the very last nibble of a given E3 frame.
Mode 4 Operation of the Transmit Payload Data Input Interface Block
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local
Loop Back
IsDS3
Internal
LOS
Enable
RESET
Direct
Mapped
ATM
Frame
Format
TimRefSel[1:0]
R/W
0
1
0
1
0
1
X
FIGURE 212. AN ILLUSTRATION OF HOW TO INTERFACE THE "SYSTEM-SIDE TERMINAL EQUIPMENT" TO THE
"TRANSMIT PAYLOAD DATA INPUT INTERFACE" BLOCK (OF THE XRT79L71) FOR MODE 4 (NIBBLE-PARALLEL/
LOOP-TIMING) OPERATION
System-Side Terminal
Equipment
XRT79L71 DS3/E3
Framer IC
E3_Data_Out[3:0]
E3_Nib_Clock_In
Tx_End_of_Frame
TxNib[3:0]
TxNibClk
TxNibFrame
NibInt
VCC
4
RxLineClk
34.368MHz
8.592MHz
TxOH_Ind
E3_Overhead_Ind