![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_125.png)
PRELIMINARY
XRT79L71
110
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: The shaded rows designate those Overhead bits that the XRT79L71 CAN insert into the outbound DS3 data-
stream. The un-shaded rows designate those Overhead bits that the XRT79L71 CANNOT insert into the outbound
DS3 data-stream.
TASK # 3: After the System-Side Terminal Equipment has waited the appropriate number of TxOHEnable
pulses from the TxOHFrame signal being sampled "High", it should assert the TxOHIns input signal by pulling
29
F0
NO
30
FEBE # 3 (C43)
YES
31
F1
NO
32
M0
NO
33
F1
NO
34
DL Bit # 1 (C51)
YES
35
F0
NO
36
DL Bit # 2 (C52)
YES
37
F0
NO
38
DL Bit # 3 (C53)
YES
39
F1
NO
40
M1
NO
41
F1
NO
42
UDL Bit # 4 (C61)
YES
43
F0
NO
44
UDL Bit # 5 (C62)
YES
45
F0
NO
46
UDL Bit # 6 (C63)
YES
47
F1
NO
48
M0
NO
49
F1
NO
50
UDL Bit # 7 (C71)
YES
51
F0
NO
52
UDL Bit # 8 (C72)
YES
53
F0
NO
54
UDL Bit # 9 (C73)
YES
55
F1
NO
TABLE 21: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE TXOHENABLE SIGNAL, SINCE THE
TXOHFRAME SIGNAL WAS LAST SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS CURRENTLY BEING
PROCESSED BY THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK
NUMBER OF PULSES IN TXOHENABLE,
SINCE
TXOHFRAME BEING SAMPLED
"HIGH"
THE OVERHEAD BIT TO BE PROCESSED
BY THE
TRANSMIT OVERHEAD DATA
INPUT INTERFACE BLOCK
CAN THIS OVERHEAD BIT BE ACCEPTED BY
THE
XRT79L71, AND INSERTED INTO THE
OUTBOUND
DS3 DATA-STREAM?